[Git][xorg-team/lib/mesa][ubuntu-artful] 152 commits: docs: add sha256 checksums for 17.2.4

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[Git][xorg-team/lib/mesa][ubuntu-artful] 152 commits: docs: add sha256 checksums for 17.2.4

Timo Aaltonen-4
GitLab

Timo Aaltonen pushed to branch ubuntu-artful at X Strike Force / lib / mesa

Commits:

  • 1b10d085
    by Andres Gomez at 2017-10-30T16:53:44+02:00
    docs: add sha256 checksums for 17.2.4
    
    Signed-off-by: Andres Gomez <[hidden email]>
    
  • e28870b9
    by Marek Olšák at 2017-11-07T18:35:53+02:00
    st/dri: don't expose modifiers in EGL if the driver doesn't implement them
    
    This unbreaks waffle/gbm (piglit/gbm) which fails initialization.
    
    v2: also don't set queryDmaBufFormats
    
    Reviewed-by: Daniel Stone <[hidden email]>
    (cherry picked from commit a65db0ad1c3ace58fbc81b6860e28c0a7645257c)
    
  • d132c0d7
    by Marek Olšák at 2017-11-07T18:35:53+02:00
    ac/surface/gfx9: don't allow DCC for the smallest mipmap levels
    
    This fixes garbage there if we don't flush TC L2 after rendering.
    
    Reviewed-by: Nicolai Hähnle <[hidden email]>
    (cherry picked from commit 759526813be137f7f139d6b4e56c5afeb8ba53c9)
    
  • e95c4af1
    by Nicolai Hähnle at 2017-11-07T18:35:53+02:00
    amd/common/gfx9: workaround DCC corruption more conservatively
    
    Fixes KHR-GL45.texture_swizzle.smoke and others on Vega.
    
    Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102809
    Cc: [hidden email]
    Reviewed-by: Marek Olšák <[hidden email]>
    (cherry picked from commit f9ccfda9bc8166f833fdb64adf1eca5b8ee69251)
    
  • 1317bdc3
    by Leo Liu at 2017-11-07T18:35:53+02:00
    radeon/video: add gfx9 offsets when rejoin the video surface
    
    For CPU access.
    
    Signed-off-by: Leo Liu <[hidden email]>
    Cc: [hidden email]
    Reviewed-by: Christian König <[hidden email]>
    (cherry picked from commit ea3dc75d72c148dabffa71e8657bfd831ad0afe9)
    
  • 9e27cdc7
    by Jason Ekstrand at 2017-11-07T18:35:53+02:00
    spirv: Claim support for the simple memory model
    
    It's rather surprising that we've never actually hit this before.
    Aparently, Ian's SPIR-V generator currently claims the Simple when you
    don't do anything complex.  We really shouldn't assert-fail on it.
    
    Reviewed-by: Ian Romanick <[hidden email]>
    Reviewed-by: Bas Nieuwenhuizen <[hidden email]>
    Cc: [hidden email]
    (cherry picked from commit 8ab9820d34d3a454e455c99e28ed2b6031b25b0f)
    
  • 78ff359d
    by Jason Ekstrand at 2017-11-07T18:35:53+02:00
    i965/blorp: Use blorp_to_isl_format for src_isl_format in blit_miptrees
    
    Reviewed-by: Topi Pohjolainen <[hidden email]>
    Cc: [hidden email]
    (cherry picked from commit 94389943b63bf8e25fecbbdf357ae5da100d2fc9)
    
  • 6dc8e69d
    by Jason Ekstrand at 2017-11-07T18:35:53+02:00
    i965/blorp: Use more temporary isl_format variables
    
    Reviewed-by: Topi Pohjolainen <[hidden email]>
    Cc: [hidden email]
    (cherry picked from commit 78e50185d6f9546f8b09cf281f5e5a17195a7ee5)
    
  • e7ddddc9
    by Jason Ekstrand at 2017-11-07T18:35:53+02:00
    i965/miptree: Take an isl_format in render_aux_usage
    
    Not all rendering matches the miptree format.  We allow rendering to
    texture views so there are cases where it may not match.  In those
    cases, our current scheme of just passing the value of ctx->sRGBEnabled
    isn't viable.  Instead, just do what we do for texturing and pass the
    view format in directly.
    
    Reviewed-by: Topi Pohjolainen <[hidden email]>
    Cc: [hidden email]
    (cherry picked from commit 39c5c12f8fbee9eec26a627f247d1f3ef7d4bf39)
    [Andres Gomez: remove code which was trivially modified previously]
    Signed-off-by: Andres Gomez <[hidden email]>
    
    Conflicts:
    	src/mesa/drivers/dri/i965/brw_draw.c
    	src/mesa/drivers/dri/i965/brw_wm_surface_state.c
    
  • 71ea4147
    by Tapani Pälli at 2017-11-07T18:35:53+02:00
    i965: unref push_const_bo in intelDestroyContext
    
    Valgrind shows that leak is caused by gen6_upload_push_constant, add
    unref push_const_bo per stage to destructor to fix this (like done for
    scratch_bo).
    
       ==10952== 144 bytes in 1 blocks are definitely lost in loss record 44 of 66
       ==10952==    at 0x4C30A1E: calloc (vg_replace_malloc.c:711)
       ==10952==    by 0x8C02847: bo_alloc_internal.constprop.10 (brw_bufmgr.c:344)
       ==10952==    by 0x8C425C4: intel_upload_space (intel_upload.c:101)
       ==10952==    by 0x8C22ED0: gen6_upload_push_constants (gen6_constant_state.c:154)
    
    v2: remove if conditions, brw_bo_unreference handles NULL (Ken, Emil)
    
    Fixes: 24891d7c05 ("i965: Store per-stage push constant BO pointers.")
    Signed-off-by: Tapani Pälli <[hidden email]>
    Reviewed-by: Emil Velikov <[hidden email]>
    Reviewed-by: Kenneth Graunke <[hidden email]>
    Cc: [hidden email]
    (cherry picked from commit 0b131ca427d788ae08426bdeddb8f4bd3c7da202)
    
  • 67fc6d43
    by Kenneth Graunke at 2017-11-07T18:35:53+02:00
    mesa: Accept GL_BACK in get_fb0_attachment with ARB_ES3_1_compatibility.
    
    According to the ARB_ES3_1_compatibility specification,
    glGetFramebufferAttachmentParameteriv is supposed to accept BACK,
    and it behaves exactly like BACK_LEFT.
    
    Fixes a GL error in GFXBench 5 Aztec Ruins.
    
    Cc: "17.3 17.2" <[hidden email]>
    Reviewed-by: Tapani Pälli <[hidden email]>
    (cherry picked from commit 4f538c3f99b25dc96cd20314ce7785fd4d333be1)
    
  • 3d7546a3
    by Topi Pohjolainen at 2017-11-07T18:35:53+02:00
    intel/compiler/gen9: Pixel shader header only workaround
    
    Fixes intermittent GPU hangs on Broxton with an Intel internal
    test case.
    
    There are plenty of similar fragment shaders in piglit that do
    not use any varyings and any uniforms. According to the
    documentation special timing is needed between pipeline stages.
    Apparently we just don't hit that with piglit. Even with the
    failing test case one doesn't always get the hang.
    
    Moreover, according to the error states the hang happens
    significantly later than the execution of the problematic shader.
    There are multiple render cycles (primitive submissions) in between.
    I've also seen error states where the ACTHD points outside the
    batch. Almost as if the hardware writes somewhere that gets used
    later on. That would also explain why piglit doesn't suffer from
    this - most tests kick off one render cycle and any corruption
    is left unseen.
    
    v2 (Ken): Instead of enabling push constants, enable one of the
              inputs (PSIZ).
    v3 (Ken, Jason): Use LAYER instead making vulkan emit_3dstate_sbe()
                     happy.
    
    Cc: "17.3 17.2" <[hidden email]>
    Reviewed-by: Kenneth Graunke <[hidden email]>
    Signed-off-by: Topi Pohjolainen <[hidden email]>
    (cherry picked from commit 97e01adfd549c260efd615289938265306d42a05)
    
  • af1dc1cf
    by Nanley Chery at 2017-11-07T18:35:53+02:00
    i965: Check CCS_E compatibility for texture view rendering
    
    Only use CCS_E to render to a texture that is CCS_E-compatible with the
    original texture's miptree (linear) format. This prevents render
    operations from writing data that can't be decoded with the original
    miptree format.
    
    On Gen10, with the new CCS_E-enabled formats handled, this enables the
    driver to pass the arb_texture_view-rendering-formats piglit test.
    
    v2. Add a TODO for texturing. (Jason)
    
    Cc: <[hidden email]>
    Signed-off-by: Nanley Chery <[hidden email]>
    Reviewed-by: Jason Ekstrand <[hidden email]>
    (cherry picked from commit 9e849eb8bb97259136b40dc2b06f42a81cfd3dae)
    
  • f33f5e9a
    by Neil Roberts at 2017-11-07T18:35:53+02:00
    nir/opt_intrinsics: Fix values for gl_SubGroupG{e,t}MaskARB
    
    Previously the values were calculated by just shifting ~0 by the
    invocation ID. This would end up including bits that are higher than
    gl_SubGroupSizeARB. The corresponding CTS test effectively requires that
    these high bits be zero so it was failing. There is a Piglit test as
    well but this appears to checking the wrong values so it passes.
    
    For the two greater-than bitmasks, this patch adds an extra mask with
    (~0>>(64-gl_SubGroupSizeARB)) to force these bits to zero.
    
    Fixes: KHR-GL45.shader_ballot_tests.ShaderBallotBitmasks
    
    Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102680#c3
    Reviewed-by: Jason Ekstrand <[hidden email]>
    Cc: [hidden email]
    Signed-off-by: Neil Roberts <[hidden email]>
    (cherry picked from commit b697ece10aa041b8653eb184d73dcf5b846729a3)
    
  • 71a33028
    by Gert Wollny at 2017-11-07T18:35:53+02:00
    r600/sb: bail out if prepare_alu_group() doesn't find a proper scheduling
    
    It is possible that the optimizer ends up in an infinite loop in
    post_scheduler::schedule_alu(), because post_scheduler::prepare_alu_group()
    does not find a proper scheduling. This can be deducted from
    pending.count() being larger than zero and not getting smaller.
    
    This patch works around this problem by signalling this failure so that the
    optimizers bails out and the un-optimized shader is used.
    
    Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103142
    Cc: <[hidden email]>
    Signed-off-by: Gert Wollny <[hidden email]>
    Signed-off-by: Dave Airlie <[hidden email]>
    (cherry picked from commit 69eee511c631a8372803f175bd6f5a9551230424)
    
  • 388b68a6
    by Eric Engestrom at 2017-11-07T18:35:54+02:00
    vc4: fix release build
    
    Mesa's DEBUG and assert's NDEBUG are not tied to each other, so we need
    to explicitly compile this code out.
    
    Fixes: 3df78928786134874eafa "vc4: Drop reloc_count tracking for debug
           asserts on non-debug builds."
    Cc: Eric Anholt <[hidden email]>
    Signed-off-by: Eric Engestrom <[hidden email]>
    Reviewed-by: Eric Anholt <[hidden email]>
    (cherry picked from commit 5d44e35a8f3967b40db153fdcedb9294d44ae5c4)
    
  • bd2037da
    by Bas Nieuwenhuizen at 2017-11-07T18:35:54+02:00
    radv: Don't expose heaps with 0 memory.
    
    It confuses CTS. This pregenerates the heap info into the
    physical device, so we can use it for translating contiguous
    indices into our "standard" ones.
    
    This also makes the WSI a bit smarter in case the first preferred
    heap does not exist.
    
    Reviewed-by: Dave Airlie <[hidden email]>
    CC: <[hidden email]>
    (cherry picked from commit 806721429afa090380bf39a4958fe4e21c63816c)
    [Andres Gomez: resolve trivial conflicts]
    Signed-off-by: Andres Gomez <[hidden email]>
    
    Conflicts:
    	src/amd/vulkan/radv_device.c
    	src/amd/vulkan/radv_private.h
    	src/amd/vulkan/radv_wsi.c
    
  • d8e0f66b
    by Dave Airlie at 2017-11-07T18:35:54+02:00
    i915g: make gears run again.
    
    We need to validate some structs exist before we dirty the states, and
    avoid the problem in some other places.
    
    Fixes: e027935a7 ("st/mesa: don't update unrelated states in non-draw calls such as Clear")
    (cherry picked from commit cc69f2385ee5405cd1bef746d3e9006fc5430545)
    
  • 23eaeeb8
    by Dave Airlie at 2017-11-07T18:35:54+02:00
    radv: free attachments on end command buffer.
    
    If we allocate attachments in the begin command buffer due to the
    render pass continue bit, we were leaking them.
    
    Since renderpasses inside a cmd buffer malloc/free these properly,
    and set to NULL, we just need to call free at end.
    
    Fixes a memory leak with multithreading demo.
    
    Reviewed-by: Bas Nieuwenhuizen <[hidden email]>
    Cc: "17.2 17.3" <[hidden email]>
    Signed-off-by: Dave Airlie <[hidden email]>
    (cherry picked from commit f0ae06a13c1a60f58de77401f705eaf620b5b822)
    [Andres Gomez: resolve trivial conflicts]
    Signed-off-by: Andres Gomez <[hidden email]>
    
    Conflicts:
    	src/amd/vulkan/radv_cmd_buffer.c
    
  • 0b0b7f18
    by Dave Airlie at 2017-11-07T18:35:54+02:00
    radv: add initial copy descriptor support. (v2)
    
    It appears the latest dota2 vulkan uses this,
    and we get a hang in VR mode without it.
    
    v2: remove finishme I left in after finishing.
    
    Reviewed-by: Bas Nieuwenhuizen <[hidden email]>
    Reviewed-by: Andres Rodriguez <[hidden email]>
    Cc: "17.2 17.3" <[hidden email]>
    Signed-off-by: Dave Airlie <[hidden email]>
    (cherry picked from commit 4bcb48b8319fd8185a326bbd1f77191bddd35506)
    
  • 662cff8f
    by Timothy Arceri at 2017-11-07T18:35:54+02:00
    radv: copy indirect lowering settings from radeonsi
    
    It looks the original indirect mask was probably copied from
    ANV.
    
    Sascha Willems demo results:
    
    tessellation ~4000 -> ~4200 fps
    
    V2: continue lowering local indirects due to llvm deficiencies.
    
    (cherry picked from commit 087e010b2b3dd83a539f97203909d6c43b5da87c)
    [Bas Nieuwenhuizen: patch is a backport for 17.2 of the cherry-pick above]
    
  • 9ba45e7d
    by Bas Nieuwenhuizen at 2017-11-07T18:35:54+02:00
    radv: Don't use vgpr indexing for outputs on GFX9.
    
    Due to LLVM bugs. Fixes a bunch of dEQP-VK.glsl.indexing.*
    tests.
    
    Fixes: e38685cc62e 'Revert "radv: disable support for VEGA for now."'
    Reviewed-by: Dave Airlie <[hidden email]>
    (cherry picked from commit 6ce550453f1df64caeb956f215d32da96b89f2b1)
    [Bas Nieuwenhuizen: resolve conflicts]
    
    Conflicts:
            src/amd/vulkan/radv_shader.c
    
  • 6a734585
    by Bas Nieuwenhuizen at 2017-11-07T18:35:54+02:00
    radv: Disallow indirect outputs for GS on GFX9 as well.
    
    Since it also uses the output vector before writing to memory.
    
    Fixes: e38685cc62e 'Revert "radv: disable support for VEGA for now."'
    Reviewed-by: Dave Airlie <[hidden email]>
    Reviewed-by: Timothy Arceri <[hidden email]>
    (cherry picked from commit c07d719e8b683e1bf78f187dd17fe4716f4e5e9c)
    [Bas Nieuwenhuizen: resolve conflicts]
    
    Conflicts:
            src/amd/vulkan/radv_shader.c
    
  • fd0cf2c9
    by Tomasz Figa at 2017-11-07T18:35:54+02:00
    glsl: Allow precision mismatch on dead data with GLSL ES 1.00
    
    Commit 259fc505454ea6a67aeacf6cdebf1398d9947759 added linker error for
    mismatching uniform precision, as required by GLES 3.0 specification and
    conformance test-suite.
    
    Several Android applications, including Forge of Empires, have shaders
    which violate this rule, on a dead varying that will be eliminated.
    The problem affects a big number of applications using Cocos2D engine
    and other GLES implementations accept this, this poses a serious
    application compatibility issue.
    
    Starting from GLSL ES 3.0, declarations with conflicting precision
    qualifiers are explicitly prohibited. However GLSL ES 1.00 does not
    clearly specify the behavior, except that
    
      "Uniforms are defined to behave as if they are using the same storage in
      the vertex and fragment processors and may be implemented this way.
      If uniforms are used in both the vertex and fragment shaders, developers
      should be warned if the precisions are different. Conversion of
      precision should never be implicit."
    
    The word "used" is not clear in this context and might refer to
     1) declared (same as GLES 3.x)
     2) referred after post-processing, or
     3) linked after all optimizations are done.
    
    Looking at existing applications, 2) or 3) seems to be widely adopted.
    To avoid compatibility issues, turn the error into a warning if GLSL ES
    version is lower than 3.0 and the data is dead in at least one of the
    shaders.
    
    Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97532
    Signed-off-by: Tomasz Figa <[hidden email]>
    Reviewed-by: Kenneth Graunke <[hidden email]>
    (cherry picked from commit 0886be093fb871b0b6169718277e0f4d18df3ea7)
    
  • 0d91d135
    by Andres Gomez at 2017-11-07T18:35:54+02:00
    cherry-ignore: radv: copy indirect lowering settings from radeonsi
    
    fixes: remove 6ce550453f1 and 059434e1763, which were depending in now
    backported 087e010b2b3.
    
    Signed-off-by: Andres Gomez <[hidden email]>
    
  • 526ecbe4
    by Andres Gomez at 2017-11-07T18:42:55+02:00
    cherry-ignore: i965: fix blorp stage_prog_data->param leak
    
    stable: This commit addressed earlier commit 8d90e28839 which did not
    land in branch.
    
    Signed-off-by: Andres Gomez <[hidden email]>
    
  • b5dc8c43
    by Andres Gomez at 2017-11-07T18:44:38+02:00
    cherry-ignore: etnaviv: don't do resolve-in-place without valid TS
    
    stable: This commit addressed earlier commit 78ade659569 which did not
    land in branch.
    
    Signed-off-by: Andres Gomez <[hidden email]>
    
  • 27cd0abe
    by Andres Gomez at 2017-11-07T18:44:44+02:00
    cherry-ignore: intel/fs: Alloc pull constants off mem_ctx
    
    stable: This commit addressed earlier commit 8d90e28839 which did not
    land in branch.
    
    Signed-off-by: Andres Gomez <[hidden email]>
    
  • a23bd4ea
    by Andres Gomez at 2017-11-07T18:44:48+02:00
    cherry-ignore: added 17.3 nominations.
    
    stable: 17.3 nominations only.
    
    Signed-off-by: Andres Gomez <[hidden email]>
    
  • 0195b78a
    by Andres Gomez at 2017-11-07T18:45:28+02:00
    cherry-ignore: automake: include git_sha1.h.in in release tarball
    
    fixes: This commit has more than one Fixes tag but the commit it
    addresses didn't land in branch.
    
    Signed-off-by: Andres Gomez <[hidden email]>
    
  • 2c582b4c
    by Andres Gomez at 2017-11-10T15:24:51+02:00
    Update version to 17.2.5
    
    Signed-off-by: Andres Gomez <[hidden email]>
    
  • ae52410b
    by Andres Gomez at 2017-11-10T15:33:58+02:00
    docs: add release notes for 17.2.5
    
    Signed-off-by: Andres Gomez <[hidden email]>
    
  • 96ad27f8
    by Andres Gomez at 2017-11-11T01:23:24+02:00
    docs: add sha256 checksums for 17.2.5
    
    Signed-off-by: Andres Gomez <[hidden email]>
    
  • 977cd76f
    by Jason Ekstrand at 2017-11-21T18:16:44+02:00
    intel/fs: Use ANY/ALL32 predicates in SIMD32
    
    We have ANY/ALL32 predicates and, for the most part, they work just
    fine.  (See the next commit for more details.)  Also, due to the way
    that flag registers are handled in hardware, instruction splitting is
    able to split the CMP correctly.  Specifically, that hardware looks at
    the execution group and knows to shift it's flag usage up correctly so a
    2H instruction will write to f0.1 instead of f0.0.
    
    Reviewed-by: Matt Turner <[hidden email]>
    Cc: [hidden email]
    (cherry picked from commit def013a863558a1f4735d82ef3dfa0f8261fa743)
    
  • 952225ae
    by Jason Ekstrand at 2017-11-21T18:16:44+02:00
    intel/fs: Use an explicit D type for vote any/all/eq intrinsics
    
    The any/all intrinsics return a boolean value so D or UD is the correct
    type.  Unfortunately, get_nir_dest has the annoying behavior of
    returnning a float type by default.  This causes format conversion which
    gives us -1.0f or 0.0f in the register.  If the consumer of the result
    does an integer comparison to zero, it will give you the right boolean
    value but if we do something more clever based on the 0/~0 assumption
    for booleans, this will give the wrong value.
    
    Reviewed-by: Iago Toral Quiroga <[hidden email]>
    Cc: [hidden email]
    (cherry picked from commit 1f416630079f38110910ba796f70e2b81e9ddbf4)
    
  • 00ccd785
    by Jason Ekstrand at 2017-11-21T18:16:44+02:00
    intel/fs: Use a pair of 1-wide MOVs instead of SEL for any/all
    
    For some reason, the any/all predicates don't work properly with SIMD32.
    In particular, it appears that a SEL with a QtrCtrl of 2H doesn't read
    the correct subset of the flag register and you end up getting garbage
    in the second half.  Work around this by using a pair of 1-wide MOVs and
    scattering the result.  This fixes the any/all instructions for SIMD32.
    
    Reviewed-by: Matt Turner <[hidden email]>
    Cc: [hidden email]
    (cherry picked from commit 1b8ef49f48ae3634e4903422a9d9c11864c03cb1)
    
  • 73342c30
    by Jason Ekstrand at 2017-11-21T18:16:44+02:00
    intel/eu/reg: Add a subscript() helper
    
    This is similar to the identically named fs_reg helper.
    
    Reviewed-by: Iago Toral Quiroga <[hidden email]>
    Cc: [hidden email]
    (cherry picked from commit 10e4feed39120072f38274b95e884422f72f360f)
    
  • eb14fb27
    by Jason Ekstrand at 2017-11-21T18:16:44+02:00
    intel/fs: Fix MOV_INDIRECT for 64-bit values on little-core
    
    The same workaround we need for 64-bit values on little core also takes
    care of the Ivy Bridge problem and does so a bit more efficiently so we
    can drop that code while we're here.
    
    Reviewed-by: Iago Toral Quiroga <[hidden email]>
    Cc: [hidden email]
    (cherry picked from commit fd1bcccc2de9ba6a1ad6171342a155091963c3b9)
    
  • a868bd7a
    by Jason Ekstrand at 2017-11-21T18:16:44+02:00
    intel/fs: Fix integer multiplication lowering for src/dst hazards
    
    Reviewed-by: Iago Toral Quiroga <[hidden email]>
    Cc: [hidden email]
    (cherry picked from commit d54f8ec744545673fd78f15ffce3cb4e47d4b5f1)
    
  • a2230871
    by Jason Ekstrand at 2017-11-21T18:16:44+02:00
    intel/fs: Mark 64-bit values as being contiguous
    
    This isn't often a problem , when we're in a compute shader, we must
    push the thread local ID so we decrement the amount of available push
    space by 1 and it's no longer even and 64-bit data can, in theory, span
    it.  By marking those uniforms contiguous, we ensure that they never get
    split in half between push and pull constants.
    
    Reviewed-by: Iago Toral Quiroga <[hidden email]>
    Cc: [hidden email]
    (cherry picked from commit 25f7453c9e6dc7c947b936bdac86680c332362bf)
    
  • 61401e97
    by Jason Ekstrand at 2017-11-21T18:16:44+02:00
    intel/fs: Rework zero-length URB write handling
    
    Originally we tried to handle this case based on slots_valid.  However,
    there are a number of ways that this can go wrong.  For one, we throw
    away any trailing slots which either aren't written or are set to
    VARYING_SLOT_PAD.  Second, even if PSIZ is a valid slot, we may not
    actually write anything there.  Between the lot of these, it was
    possible to end up in a case where we tried to do a regular URB write
    but ended up with a length of 1 which is invalid.  This commit moves it
    to the end and makes it based on a new boolean flag urb_written.
    
    Reviewed-by: Iago Toral Quiroga <[hidden email]>
    Cc: [hidden email]
    (cherry picked from commit 7a82ad54bb56cafaeea7f909cd9fc35542c23ba0)
    
  • 7d61bf50
    by Emil Velikov at 2017-11-21T18:16:45+02:00
    targets/opencl: don't hardcode the icd file install to /etc/...
    
    Use $(sysconfdir) instead of hardcoding /etc.
    
    While the OpenCL spec expects the file in /etc, people building their
    stack can override that, esp. !Linux users.
    
    Furthermore this removes a fundamental violation, which results in the
    system file being overwritten even as one explicitly sets --prefix
    and/or DESTDIR.
    
    Cc: [hidden email]
    Signed-off-by: Emil Velikov <[hidden email]>
    Reviewed-by: Francisco Jerez <[hidden email]>
    Reviewed-By: Aaron Watry <[hidden email]>
    (cherry picked from commit 0cd09585441d15ef1ff49de497008103f0b0e1ac)
    
  • dfa57d01
    by Kenneth Graunke at 2017-11-21T18:16:45+02:00
    i965: properly initialize brw->cs.base.stage to MESA_SHADER_COMPUTE
    
    This has a bit of a surprising effect:
    
    For the render pipeline, the upload_sampler_state_table atom emits
    3DSTATE_BINDING_TABLE_POINTERS_XS.  It tries to avoid this for compute:
    
       if (GEN_GEN >= 7 && stage_state->stage != MESA_SHADER_COMPUTE) {
          /* Emit a 3DSTATE_SAMPLER_STATE_POINTERS_XS packet. */
          genX(emit_sampler_state_pointers_xs)(brw, stage_state);
       } ...
    
    However, we were failing to initialize brw->cs.base.stage, so it was
    left as 0 (MESA_SHADER_VERTEX), causing this condition to break.  We
    then emitted 3DSTATE_SAMPLER_STATE_POINTERS_VS in GPGPU mode, when
    trying to upload CS samplers.  Nothing good can come of this.
    
    Found by inspection while debugging a GPU hang.  Jordan believes this
    helps the Deus Ex: Mankind Divided benchmark mode's stability when
    running with shader cache.
    
    Cc: [hidden email]
    Reviewed-by: Jason Ekstrand <[hidden email]>
    Reviewed-by: Jordan Justen <[hidden email]>
    (cherry picked from commit a16dc04ad51c32e5c7d136e4dd6273d983385d3f)
    [Andres Gomez: resolve trivial conflicts]
    Signed-off-by: Andres Gomez <[hidden email]>
    
    Conflicts:
    	src/mesa/drivers/dri/i965/brw_context.c
    
  • 386cc0c6
    by Timothy Arceri at 2017-11-21T18:16:45+02:00
    glsl: drop cache_fallback
    
    This turned out to be a dead end, it is much easier and less error
    prone to just cache the IR used by the drivers backend e.g. TGSI or
    NIR.
    
    Cc: "17.2 17.3" <[hidden email]>
    Reviewed-by: Tapani Pälli <[hidden email]>
    Reviewed-by: Kenneth Graunke <[hidden email]>
    (cherry picked from commit cf05bb506a075c9e3b8a3c374b928ff0367c49b2)
    
  • 96fe2da8
    by Timothy Arceri at 2017-11-21T18:16:45+02:00
    glsl: use the correct parent when allocating program data members
    
    Cc: "17.2 17.3" <[hidden email]>
    Reviewed-by: Tapani Pälli <[hidden email]>
    Reviewed-by: Kenneth Graunke <[hidden email]>
    (cherry picked from commit 9c33533586476693a197b7179552d140d54f23f2)
    
  • 731076f0
    by Timothy Arceri at 2017-11-21T18:16:45+02:00
    mesa: rework how we free gl_shader_program_data
    
    When I introduced gl_shader_program_data one of the intentions was to
    fix a bug where a failed linking attempt freed data required by a
    currently active program. However I seem to have failed to finish
    hooking up the final steps required to have the data hang around.
    
    Here we create a fresh instance of gl_shader_program_data every
    time we link. gl_program has a reference to gl_shader_program_data
    so it will be freed once the program is no longer active.
    
    Cc: "17.2 17.3" <[hidden email]>
    Reviewed-by: Tapani Pälli <[hidden email]>
    Reviewed-by: Neil Roberts <[hidden email]>
    Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102177
    (cherry picked from commit 6a72eba755fea15a0d97abb913a6315d9d32e274)
    
  • 3ca2b007
    by Neil Roberts at 2017-11-21T18:16:45+02:00
    glsl: Transform fb buffers are only active if a variable uses them
    
    The GL spec will soon be revised to clarify that a buffer binding for
    a transform feedback buffer is only required if a variable is actually
    defined to use the buffer binding point. Previously a declaration for
    the default transform buffer would make it require a binding even if
    nothing was declared to use the default buffer.
    
    Affects:
    KHR-GL44/45.enhanced_layouts.xfb_stride_of_empty_list
    KHR-GL44/45.enhanced_layouts.xfb_stride_of_empty_list_and_api
    
    Reviewed-by: Nicolai Hähnle <[hidden email]>
    Cc: [hidden email]
    (cherry picked from commit 4dc8458cd13154daa48bd97c3f8393daf02aa351)
    
  • c7e12a3a
    by Emil Velikov at 2017-11-21T18:16:45+02:00
    configure.ac: loosen --enable-glvnd check to honour egl
    
    Currently we error out when building GLVND w/o GLX.
    
    That was the original premice before we had EGL. As the commit says,
    that error should be reworked to honour both - do so.
    
    v2: Drop noop *);; (Eric)
    
    Reported-by: Lukas Rusak <[hidden email]>
    Fixes: ce562f9e3fa ("EGL: Implement the libglvnd interface for EGL (v3)")
    Signed-off-by: Emil Velikov <[hidden email]>
    Reviewed-by: Eric Engestrom <[hidden email]>
    Tested-by: Lukas Rusak <[hidden email]> (v1)
    (cherry picked from commit b4967561c035182b64d3ae0f474d4ef281535ce1)
    
  • a3adb738
    by Emil Velikov at 2017-11-21T18:16:45+02:00
    configure.ac: require xcb* for the omx/va/... when using x11 platform
    
    Targets such as omx and va can work w/o anything X related. Mandate the
    xcb* dependencies only when the X11 platform is selected.
    
    Reported-by: Lukas Rusak <[hidden email]>
    Fixes: 63e11ac2b5c ("configure: error out if building VA w/o supported
    platform")
    Signed-off-by: Emil Velikov <[hidden email]>
    Reviewed-by: Eric Engestrom <[hidden email]>
    Tested-by: Lukas Rusak <[hidden email]> (v1)
    (cherry picked from commit 85a017230cacd0661570421c8e5b0619e512d33d)
    
  • 9d49fd74
    by Alex Smith at 2017-11-21T18:16:45+02:00
    spirv: Use correct type for sampled images
    
    We should use the result type of the OpSampledImage opcode, rather than
    the type of the underlying image/samplers.
    
    This resolves an issue when using separate images and shadow samplers
    with glslang. Example:
    
        layout (...) uniform samplerShadow s0;
        layout (...) uniform texture2D res0;
        ...
        float result = textureLod(sampler2DShadow(res0, s0), uv, 0);
    
    For this, for the combined OpSampledImage, the type of the base image
    was being used (which does not have the Depth flag set, whereas the
    result type does), therefore it was not being recognised as a shadow
    sampler. This led to the wrong LLVM intrinsics being emitted by RADV.
    
    Signed-off-by: Alex Smith <[hidden email]>
    Cc: "17.2 17.3" <[hidden email]>
    Reviewed-by: Jason Ekstrand <[hidden email]>
    (cherry picked from commit e9eb3c4753e4f56b03d16d8d6f71d49f1e7b97db)
    
  • 2c9d7204
    by Alex Smith at 2017-11-21T18:16:45+02:00
    nir/spirv: tg4 requires a sampler
    
    Gather operations in both GLSL and SPIR-V require a sampler. Fixes
    gathers returning garbage when using separate texture/samplers (on AMD,
    was using an invalid sampler descriptor).
    
    Signed-off-by: Alex Smith <[hidden email]>
    Cc: "17.2 17.3" <[hidden email]>
    Reviewed-by: Jason Ekstrand <[hidden email]>
    (cherry picked from commit 4122d008466cef47eaa3f958924618060f4e4330)
    
  • d53558fd
    by Adam Jackson at 2017-11-21T18:16:45+02:00
    glx/drisw: Fix glXMakeCurrent(dpy, None, ctx)
    
    This is perfectly legal in GL 3.0+.
    
    Fixes piglit/glx-create-context-current-no-framebuffer.
    
    Cc: [hidden email]
    Reviewed-by: Tapani Pälli <[hidden email]>
    Reviewed-by: Emil Velikov <[hidden email]>
    Signed-off-by: Adam Jackson <[hidden email]>
    (cherry picked from commit 033cfb17db85b38bc012d74f30f6c92cddf85216)
    
  • 167f50ae
    by Adam Jackson at 2017-11-21T18:16:45+02:00
    glx/dri3: Fix passing renderType into glXCreateContext
    
    Without this, trying to create a GLX_RGBA_FLOAT_TYPE_ARB context would
    fail, because GLX_RGBA_TYPE would be a mismatch with the fbconfig.
    
    Cc: [hidden email]
    Reviewed-by: Tapani Pälli <[hidden email]>
    Reviewed-by: Emil Velikov <[hidden email]>
    Signed-off-by: Adam Jackson <[hidden email]>
    (cherry picked from commit 257edb5b9aedc9fc5d5c13eb2f48a0c11d15456f)
    
  • f5e82045
    by Dylan Baker at 2017-11-21T18:16:45+02:00
    autotools: Set C++ visibility flags on Intel
    
    These flags are set for C sources, but not C++. This causes symbol
    visibility leaks from the C++ parts of the Intel compiler.
    
    Fixes: 700bebb958e93f4d ("i965: Move the back-end compiler to src/intel/compiler")
    Signed-off-by: Dylan Baker <[hidden email]>
    Reviewed-by: Matt Turner <[hidden email]>
    (cherry picked from commit 854455498c0370e959c0bb25680641e05faea3e2)
    
  • 9229774b
    by Kenneth Graunke at 2017-11-21T18:16:45+02:00
    i965: Make L3 configuration atom listen for TCS/TES program updates.
    
    The L3 configuration code already considers the TCS and TES programs,
    but failed to listen for TCS/TES program changes.
    
    This was somehow missing.
    
    Fixes: e9644cb1f96ccf7e ("i965: Consider tessellation in get_pipeline_state_l3_weights.")
    Reviewed-by: Francisco Jerez <[hidden email]>
    (cherry picked from commit b8d42cccd053e32ca048645ea7e6f901366e286d)
    
  • 0465cfe0
    by Kenneth Graunke at 2017-11-21T18:16:46+02:00
    intel/tools: Fix detection of enabled shader stages.
    
    We renamed "Function Enable" to "Enable", which broke our detection
    of whether shaders are enabled or not.  So, we'd see a bunch of HS/DS
    packets with program offsets of 0, and think that was a valid TCS/TES.
    
    Fixes: c032cae9ff77e (genxml: Rename "Function Enable" to "Enable".)
    
    Reviewed-by: Lionel Landwerlin <[hidden email]>
    (cherry picked from commit 9a0465b3a3a1a6e8beda7a59506c2e1a1aae776f)
    
  • 84f765ce
    by Dave Airlie at 2017-11-21T18:16:46+02:00
    r600: fix isoline tess factor component swapping.
    
    As per radeonsi, the tess factor components for isolines
    are reversed.
    
    Fixes: tests/spec/arb_tessellation_shader/execution/isoline.shader_test
    Cc: <[hidden email]>
    Signed-off-by: Dave Airlie <[hidden email]>
    (cherry picked from commit f3f8615d76b20ad66466b172a600e06b9a833729)
    
  • 179acf65
    by Jason Ekstrand at 2017-11-21T18:16:46+02:00
    i965: Add stencil buffers to cache set regardless of stencil texturing
    
    We may access them as a texture using blorp regardless of whether or not
    stencil texturing is enabled.
    
    Reviewed-by: Kenneth Graunke <[hidden email]>
    Cc: [hidden email]
    (cherry picked from commit 6830ba0d3be8df12572622839743c41b4f294825)
    
  • 75efb540
    by Bas Nieuwenhuizen at 2017-11-21T18:16:46+02:00
    radv: Free syncobj with multiple imports.
    
    Otherwise we can leak the old syncobj.
    
    Fixes: eaa56eab6da "radv: initial support for shared semaphores (v2)"
    Reviewed-by: Dave Airlie <[hidden email]>
    Reviewed-by: Samuel Pitoiset <[hidden email]>
    (cherry picked from commit 917d3b43f2b206ccf036542aa1c39f1dbdd84f62)
    
  • 25673368
    by Bas Nieuwenhuizen at 2017-11-21T18:16:46+02:00
    radv: Free temporary syncobj after waiting on it.
    
    Otherwise we leak it.
    
    Fixes: eaa56eab6da "radv: initial support for shared semaphores (v2)"
    Reviewed-by: Samuel Pitoiset <[hidden email]>
    (cherry picked from commit 7c255788637b8fdfc31aca5f7891f39a110c5cb2)
    
  • 0f4dfee2
    by Tim Rowley at 2017-11-21T18:16:46+02:00
    swr/rast: Use gather instruction for i32gather_ps on simd16/avx512
    
    Speed up avx512 platforms; fixes performance regression caused
    by swithc to simdlib.
    
    Reviewed-by: Bruce Cherniak <[hidden email]>
    Cc: [hidden email]
    (cherry picked from commit 439904847e9c2970494c18e8c47bd6c38c0ed8ab)
    
  • 8edbc8f1
    by Tim Rowley at 2017-11-21T18:16:46+02:00
    swr/rast: Faster emulated simd16 permute
    
    Speed up simd16 frontend (default) on avx/avx2 platforms;
    fixes performance regression caused by switch to simdlib.
    
    Reviewed-by: Bruce Cherniak <[hidden email]>
    Cc: [hidden email]
    (cherry picked from commit d8489517a572c7e5c5405ebf510db9d20b1e2591)
    
  • 653a2039
    by Anuj Phogat at 2017-11-21T18:16:46+02:00
    i965: Program DWord Length in MI_FLUSH_DW
    
    Signed-off-by: Anuj Phogat <[hidden email]>
    Cc: <[hidden email]>
    (cherry picked from commit 6165fda59b889de035b38d9a1a08ffe0da19e6a6)
    
    Squashed with:
    
    i965: Remove DWord length from MI_FLUSH_DW definition
    
    Fixes: 6165fda59b8 ("i965: Program DWord Length in MI_FLUSH_DW")
    Cc: <[hidden email]>
    Signed-off-by: Anuj Phogat <[hidden email]>
    Reviewed-by: Nanley Chery <[hidden email]>
    Reviewed-by: Kenneth Graunke <[hidden email]>
    (cherry picked from commit 822fd2341db49cbbe813114d2d0fc1b66de4807c)
    
  • 82876e24
    by Anuj Phogat at 2017-11-21T18:16:46+02:00
    i965/gen8+: Fix the number of dwords programmed in MI_FLUSH_DW
    
    Number of dwords in MI_FLUSH_DW changed from 4 to 5 in gen8+.
    
    Signed-off-by: Anuj Phogat <[hidden email]>
    Cc: <[hidden email]>
    (cherry picked from commit 1dc45d75bb3ff3085f7356b8ec658111529ff76d)
    [Andres Gomez: brw->gen not yet dropped in favor of devinfo->gen]
    Signed-off-by: Andres Gomez <[hidden email]>
    
    Conflicts:
    	src/mesa/drivers/dri/i965/brw_pipe_control.c
    	src/mesa/drivers/dri/i965/intel_blit.c
    
  • 70b1c115
    by Matt Turner at 2017-11-21T18:16:46+02:00
    i965/fs: Fix extract_i8/u8 to a 64-bit destination
    
    The MOV instruction can extract bytes to words/double words, and
    words/double words to quadwords, but not byte to quadwords.
    
    For unsigned byte to quadword, we can read them as words and AND off the
    high byte and extract to quadword in one instruction. For signed bytes,
    we need to first sign extend to word and the sign extend that word to a
    quadword.
    
    Fixes the following test on CHV, BXT, and GLK:
       KHR-GL46.shader_ballot_tests.ShaderBallotBitmasks
    Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103628
    Reviewed-by: Jason Ekstrand <[hidden email]>
    
    (cherry picked from commit 6ac2d16901927013393f873a34c717ece5014c1a)
    
  • b3410696
    by Matt Turner at 2017-11-21T18:16:46+02:00
    i965/fs: Split all 32->64-bit MOVs on CHV, BXT, GLK
    
    Fixes the following tests on CHV, BXT, and GLK:
        KHR-GL46.shader_ballot_tests.ShaderBallotFunctionBallot
        dEQP-VK.spirv_assembly.instruction.compute.uconvert.uint32_to_int64
    Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103115
    
    (cherry picked from commit cfcfa0b9cd1b1d563a988b1250950057c4612ac9)
    
  • f288607e
    by Kenneth Graunke at 2017-11-22T18:41:18+02:00
    i965: Implement another VF cache invalidate workaround on Gen8+.
    
    ...and provide a better citation for the existing one.
    
    v2:
    - Apply the workaround to Gen8 too, as intended (caught by Topi).
    - Restructure to add bits instead of an extra flush (based on a similar
      patch by Rafael Antognolli).
    
    Cc: [hidden email]
    Reviewed-by: Rafael Antognolli <[hidden email]>
    (cherry picked from commit 8d48671492412e04c18651a779cabacf30ed0afe)
    [Andres Gomez: brw->gen not yet dropped in favor of devinfo->gen]
    Signed-off-by: Andres Gomez <[hidden email]>
    
    Conflicts:
    	src/mesa/drivers/dri/i965/brw_pipe_control.c
    
    Squashed with:
    
    i965: Revert Gen8 aspect of VF PIPE_CONTROL workaround.
    
    This apparently causes hangs on Broadwell, so let's back it out for now.
    I think there are other PIPE_CONTROL workarounds that we're missing.
    
    Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103787
    (cherry picked from commit a01ba366e01b7d1cdfa6b0e6647536b10c0667ef)
    [Andres Gomez: brw->gen not yet dropped in favor of devinfo->gen]
    Signed-off-by: Andres Gomez <[hidden email]>
    
    Conflicts:
    	src/mesa/drivers/dri/i965/brw_pipe_control.c
    
  • 0d02e91c
    by Derek Foreman at 2017-11-22T18:41:23+02:00
    egl/wayland: Add a fallback when fourcc query isn't supported
    
    When queryImage doesn't support __DRI_IMAGE_ATTRIB_FOURCC wayland clients
    will die with a NULL derefence in wl_proxy_add_listener.
    
    Attempt to provide a simple fallback to keep ancient systems working.
    
    Fixes: 6595c699511 ("egl/wayland: Remove more surface specifics from
    create_wl_buffer")
    Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103519
    Signed-off-by: Derek Foreman <[hidden email]>
    Reviewed-by: Emil Velikov <[hidden email]>
    Acked-by: Daniel Stone <[hidden email]>
    Reviewed-by: Eric Engestrom <[hidden email]>
    (cherry picked from commit 0db36caa192b129cb4f22d152f82f38fcf6f06d4)
    
    Squashed with:
    
    egl: fix var type
    
    queryImage() takes an `int*`; compiler is warning about the
    signed<->unsigned pointer mismatch.
    
    Fixes: 0db36caa192b129cb4f2 "egl/wayland: Add a fallback when fourcc
           query isn't supported"
    Signed-off-by: Eric Engestrom <[hidden email]>
    Reviewed-by: Frank Binns <[hidden email]>
    Reviewed-by: Tapani Pälli <[hidden email]>
    Reviewed-by: Emil Velikov <[hidden email]>
    Reviewed-by: Derek Foreman <[hidden email]>
    (cherry picked from commit ca95d7ad4e1b900eb3d559ed5bda0b96b232961d)
    
  • a4456581
    by Kenneth Graunke at 2017-11-22T18:41:23+02:00
    i965: Upload invariant state once at the start of the batch on Gen4-5.
    
    We want to emit invariant state at the start of a render batch.  In the
    past, this more or less happened: a new batch flagged BRW_NEW_CONTEXT
    (because we don't have hardware contexts), which triggered the
    brw_invariant_state atom.  So, it would be emitted before any 3D
    drawing.  (Technically, there might be some BLT commands in the batch
    because Gen4-5 have a single combined render/BLT ring, but that should
    be harmless).
    
    With the advent of BLORP, this broke.  The first item in a batch might
    be a BLORP operation, which bypasses the normal draw upload path.  So,
    we need to ensure invariant state happens first.  To do that, we just
    upload it when creating a new batch.  On Gen6+ we'd need to worry about
    whether it's a RENDER or BLT batch, but because we have a combined ring,
    this approach should work fine on Gen4-5.
    
    Seems to fix GPU hangs when playing hardware accelerated video with
    mpv -hwdec=vaapi on Ironlake.
    
    Cc: [hidden email]
    Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103529
    Reviewed-by: Jason Ekstrand <[hidden email]>
    (cherry picked from commit 8f91aa35a54e127b68415376ef2b577ea8fc30f9)
    
  • ae629ca8
    by George Barrett at 2017-11-22T18:41:23+02:00
    glsl: Catch subscripted calls to undeclared subroutines
    
    generate_array_index fails to check whether the target of a subroutine
    call exists in the AST, potentially passing around null ir_rvalue
    pointers eventuating in abort/segfault.
    
    Fixes: fd01840c0bd3 ("glsl: add AoA support to subroutines")
    Reviewed-by: Timothy Arceri <[hidden email]>
    Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=100438
    (cherry picked from commit f09c2cefdd53cd61562a994294e9d0630868d2da)
    
  • 49277c6e
    by Nicolai Hähnle at 2017-11-22T18:41:23+02:00
    ddebug: fix use-after-free of streamout targets
    
    Fixes: b47727a83ad6 ("ddebug: implement pipelined hang detection mode")
    Reviewed-by: Marek Olšák <[hidden email]>
    (cherry picked from commit 16f8da299700e714fd5aff265b8f28fe2badfa95)
    
  • f562d930
    by Andres Gomez at 2017-11-22T18:41:23+02:00
    cherry-ignore: intel/fs: Use a pure vertical stride for large register strides
    
    stable: This commit is not really needed after 6ac2d169019.
    
    Signed-off-by: Andres Gomez <[hidden email]>
    
  • 010751e9
    by Andres Gomez at 2017-11-22T18:41:23+02:00
    cherry-ignore: intel/nir: Use the correct indirect lowering masks in link_shaders
    
    stable: These commits addressed earlier commit 379b24a40d3 which did
    not land in branch.
    
    Signed-off-by: Andres Gomez <[hidden email]>
    
  • 96be105d
    by Andres Gomez at 2017-11-22T18:41:23+02:00
    cherry-ignore: intel/fs: Use the original destination region for int MUL lowering
    
    stable: These commits resulted in a CTS regression being addressed at
    https://bugs.freedesktop.org/show_bug.cgi?id=103626 .
    
    Signed-off-by: Andres Gomez <[hidden email]>
    
  • d255b772
    by Andres Gomez at 2017-11-22T18:41:23+02:00
    cherry-ignore: intel/fs: refactors
    
    stable: These commits are refactorings rather than fixes.
    
    Signed-off-by: Andres Gomez <[hidden email]>
    
  • 1519933c
    by Andres Gomez at 2017-11-22T18:41:23+02:00
    cherry-ignore: r600/shader: reserve first register of vertex shader.
    
    stable: This commit addressed earlier commit ea1b97714d9b which did
    not land in branch.
    
    Signed-off-by: Andres Gomez <[hidden email]>
    
  • c9325693
    by Andres Gomez at 2017-11-22T18:41:24+02:00
    cherry-ignore: anv/cmd_buffer: Advance the address when initializing clear colors
    
    stable: This commit depends on earlier commit 3735af04152b which did
    not land in branch.
    
    Signed-off-by: Andres Gomez <[hidden email]>
    
  • 807da6e2
    by Andres Gomez at 2017-11-22T18:41:24+02:00
    cherry-ignore: anv/cmd_buffer: Take bo_offset into account in fast clear state addresses
    
    stable: This commit addressed earlier commit a62a97933578 which did
    not land in branch.
    
    Signed-off-by: Andres Gomez <[hidden email]>
    
  • 8cd5bd2a
    by Andres Gomez at 2017-11-22T18:41:24+02:00
    cherry-ignore: i965: Mark BOs as external when we export their handle
    
    stable: These commits addressed earlier commit 2c4097aff1b which did
    not land in branch.
    
    Signed-off-by: Andres Gomez <[hidden email]>
    
  • ba0f9657
    by Andres Gomez at 2017-11-22T18:41:24+02:00
    cherry-ignore: added 17.3 nominations.
    
    stable: 17.3 nominations only.
    
    Signed-off-by: Andres Gomez <[hidden email]>
    
  • f6d3eed5
    by Andres Gomez at 2017-11-22T18:41:24+02:00
    cherry-ignore: glsl: Fix typo fragement -> fragment
    
    fixes: This commit is only a typo correction on an error message.
    
    Signed-off-by: Andres Gomez <[hidden email]>
    
  • a231bbd6
    by Andres Gomez at 2017-11-22T18:41:24+02:00
    cherry-ignore: egl: pass the dri2_dpy to the $plat_teardown functions
    
    fixes: This commit makes reference to 2 other commits but none have
    made it to the 17.2 queue.
    
    Signed-off-by: Andres Gomez <[hidden email]>
    
  • 9888913a
    by Andres Gomez at 2017-11-22T18:41:24+02:00
    cherry-ignore: Revert "intel/fs: Use a pure vertical stride for large register strides"
    
    extra: The commit just references a proper fix that has already
    landed.
    
    Signed-off-by: Andres Gomez <[hidden email]>
    
  • 6f34ba40
    by Andres Gomez at 2017-11-26T01:26:34+02:00
    Update version to 17.2.6
    
    Signed-off-by: Andres Gomez <[hidden email]>
    
  • 00b52f8e
    by Andres Gomez at 2017-11-26T01:32:53+02:00
    docs: add release notes for 17.2.6
    
    Signed-off-by: Andres Gomez <[hidden email]>
    
  • 93c2beaf
    by Andres Gomez at 2017-11-26T01:40:36+02:00
    docs: add sha256 checksums for 17.2.6
    
    Signed-off-by: Andres Gomez <[hidden email]>
    
  • b9b60dbf
    by Andres Gomez at 2017-11-26T02:15:43+02:00
    docs: remove bug 103626 from fix list as per 17.2.6
    
    Bug https://bugs.freedesktop.org/show_bug.cgi?id=103626 was
    incorrectly listed as fixed.
    
    Signed-off-by: Andres Gomez <[hidden email]>
    
  • a8a5a97f
    by Ilia Mirkin at 2017-12-08T17:30:34+00:00
    glsl: fix derived cs variables
    
    There are two issues with the current implementation. First, it relies
    on the layout(local_size_*) happening in the same shader as the main
    function, and secondly it doesn't work for variable group sizes.
    
    In both cases, the simplest fix is to move the setup of these derived
    values to a later time, similar to how the gl_VertexID workarounds are
    done. There already exist system values defined for both of the derived
    values, so we use them unconditionally, and lower them after linking is
    performed.
    
    While we're at it, we move to using gl_LocalGroupSizeARB instead of
    gl_WorkGroupSize for variable group sizes.
    
    Also the dead code elimination avoidance can be removed, since there
    can be situations where gl_LocalGroupSizeARB is needed but has not been
    inserted for the shader with main function. As a result, the lowering
    code has to insert its own copies of the system values if needed.
    
    Reported-by: Stephane Chevigny <[hidden email]>
    Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103393
    Cc: [hidden email]
    Signed-off-by: Ilia Mirkin <[hidden email]>
    Reviewed-by: Jordan Justen <[hidden email]>
    Reviewed-by: Samuel Pitoiset <[hidden email]>
    (cherry picked from commit 4d24a7cb97641cacecd371d1968f6964785822e4)
    Signed-off-by: Emil Velikov <[hidden email]>
    
    Conflicts:
    	src/compiler/glsl/meson.build
    
  • c2ff8e3e
    by Gert Wollny at 2017-12-08T17:30:34+00:00
    r600: Emit EOP for more CF instruction types
    
    So far on pre-cayman chipsets the CF instructions CF_OP_LOOP_END,
    CF_OP_CALL_FS, CF_OP_POP, and CF_OP_GDS an extra CF_NOP instruction
    was added to add the EOP flag, even though this is not actually
    needed, because all these instrutions support the EOP flag.
    
    This patch removes the fixup code, adds setting the EOP flag for the
    according instructions as well as others like CF_OP_TEX and CF_OP_VTX,
    and adds writing out EOP for this type of instruction in the disassembler.
    
    This also fixes a bug where shaders were created that didn't actually have
    the EOP flag set in the last CF instruction, which might have resulted
    in GPU lockups.
    
    [airlied: cleaned up a little]
    Signed-off-by: Gert Wollny <[hidden email]>
    Cc: <[hidden email]>
    Signed-off-by: Dave Airlie <[hidden email]>
    (cherry picked from commit 1d076aafbc05b0af299826ac0ee63b2fb28e944a)
    
  • 779a028f
    by Emil Velikov at 2017-12-08T17:30:34+00:00
    gl_table.py: add extern C guard for the generated glapitable.h
    
    The header can be included from C++, hence contents should have
    appropriate notation.
    
    Cc: [hidden email]
    Cc: Dylan Baker <[hidden email]>
    Signed-off-by: Emil Velikov <[hidden email]>
    Reviewed-by: Eric Engestrom <[hidden email]>
    (cherry picked from commit c7616ac06973a80c3c6e9def49a3fa6606ba6097)
    
  • 4f97100a
    by Tapani Pälli at 2017-12-08T17:30:34+00:00
    mesa/gles: adjust internal format in glTexSubImage2D error checks
    
    When floating point textures are created on OpenGL ES 2.0, driver
    is free to choose used internal format. Mesa makes this decision in
    adjust_for_oes_float_texture. Error checking for glTexImage2D properly
    checks that sized formats are not used. We use same error checking
    path for glTexSubImage2D (since there is lot of overlap), however since
    those checks include internalFormat checks, we need to pass original
    internalFormat passed by the client. Patch adds oes_float_internal_format
    that does reverse adjust_for_oes_float_texture to get that format.
    
    Fixes following test failure:
       ES2-CTS.gtf.GL2ExtensionTests.texture_float.texture_float
    
    (when running test with MESA_GLES_VERSION_OVERRIDE=2.0)
    
    Signed-off-by: Tapani Pälli <[hidden email]>
    Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103227
    Cc: "17.3" <[hidden email]>
    Reviewed-by: Matt Turner <[hidden email]>
    (cherry picked from commit 1e508e10d9ae649bfe5ab7b1842993be50052b21)
    
  • b25baea7
    by Kai Wasserbäch at 2017-12-08T17:30:34+00:00
    docs: Point to apt.llvm.org for development snapshot packages
    
    Signed-off-by: Kai Wasserbäch <[hidden email]>
    Reviewed-by: Eric Engestrom <[hidden email]>
    (cherry picked from commit d25123e23a77e216b45f8e1a83ac32805b07be82)
    
  • ab5585ff
    by Ben Crocker at 2017-12-08T17:30:34+00:00
    docs/llvmpipe.html: Minor edits
    
    Language and spelling fixups in three places.
    
    Cc: "17.2" "17.3" <[hidden email]>
    Signed-off-by: Ben Crocker <[hidden email]>
    Reviewed-by: Eric Engestrom <[hidden email]>
    
    [Eric: move two fixes from the other patch to this one.]
    Signed-off-by: Eric Engestrom <[hidden email]>
    (cherry picked from commit b43daf7bf6cb505ece025c718ac6f074c38b2d49)
    
  • de438f15
    by Dave Airlie at 2017-12-08T17:30:34+00:00
    r600/sb: handle jump after target to end of program. (v2)
    
    This fixes hangs on cayman with
    tests/spec/arb_tessellation_shader/execution/trivial-tess-gs_no-gs-inputs.shader_test
    
    This has a single if/else in it, and when this peephole activated,
    it would set the jump target to NULL if there was no instruction
    after the final POP. This adds a NOP if we get a jump in this case,
    and seems to fix the hangs, so we have a valid target for the ELSE
    instruction to go to, instead of 0 (which causes infinite loops).
    
    v2: update last_cf correctly. (I had some other patches hide this)
    
    Cc: <[hidden email]>
    Signed-off-by: Dave Airlie <[hidden email]>
    (cherry picked from commit 579ec9c311eb5176054b624f39c5c024605b58d6)
    
  • e893ae4d
    by Marek Olšák at 2017-12-08T17:30:34+00:00
    radeonsi: fix layered DCC fast clear
    
    Cc: 17.2 17.3 <[hidden email]>
    Reviewed-by: Nicolai Hähnle <[hidden email]>
    (cherry picked from commit 6863651bbdd7dcfad60bae78d1e17898f49ca08b)
    
  • a995d6bb
    by Marek Olšák at 2017-12-08T17:30:34+00:00
    radeonsi/gfx9: fix importing shared textures with DCC
    
    VI has 11 dwords at least. GFX9 has 10 dwords.
    
    Cc: 17.2 17.3 <[hidden email]>
    Reviewed-by: Nicolai Hähnle <[hidden email]>
    (cherry picked from commit ed4780383cae61e051b3d3d120649222da49feae)
    [Emil Velikov: s|radeon/r600_texture.c|radeonsi/si_state.c|]
    Signed-off-by: Emil Velikov <[hidden email]>
    
    Conflicts:
    	src/gallium/drivers/radeon/r600_texture.c
    
  • b50154ef
    by Jason Ekstrand at 2017-12-08T18:27:00+00:00
    i965: Disable regular fast-clears (CCS_D) on gen9+
    
    This partially reverts commit 3e57e9494c2279580ad6a83ab8c065d01e7e634e
    which caused a bunch of GPU hangs on several Source titles.  To date, we
    have no clue why these hangs are actually happening.  This undoes the
    final effect of 3e57e9494c227 and gets us back to not hanging.  Tested
    with Team Fortress 2.
    
    Reviewed-by: Kenneth Graunke <[hidden email]>
    Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102435
    Fixes: 3e57e9494c2279580ad6a83ab8c065d01e7e634e
    Cc: [hidden email]
    (cherry picked from commit ee57b15ec764736e2d5360beaef9fb2045ed0f68)
    
  • 4d0ec672
    by Marek Olšák at 2017-12-08T18:27:00+00:00
    radeonsi: flush the context after resource_copy_region for buffer exports
    
    Cc: 17.2 17.3 <[hidden email]>
    Reviewed-by: Nicolai Hähnle <[hidden email]>
    (cherry picked from commit 5e805cc74bc52f97de8f6308fc06bc96623e7e09)
    [Emil Velikov: s/si_texture_disable_dcc/r600_texture_disable_dcc/]
    Signed-off-by: Emil Velikov <[hidden email]>
    
    Conflicts:
    	src/gallium/drivers/radeon/r600_texture.c
    
  • 76b54923
    by Emil Velikov at 2017-12-08T18:27:00+00:00
    cherry-ignore: radeonsi: allow DMABUF exports for local buffers
    
    Commit depends on at least 8b3a2578519, which did not land in branch.
    
    Signed-off-by: Emil Velikov <[hidden email]>
    
  • b3b08d53
    by Gert Wollny at 2017-12-08T18:27:00+00:00
    r600/sb: do not convert if-blocks that contain indirect array access
    
    If an array is accessed within an if block, then currently it is not known
    whether the value in the address register is involved in the evaluation of the
    if condition, and converting the if condition may actually result in
    out-of-bounds array access. Consequently, if blocks that contain indirect array
    access should not be converted.
    
    Fixes piglits on r600/BARTS:
    spec/glsl-1.10/execution/variable-indexing/
      vs-output-array-float-index-wr
      vs-output-array-vec3-index-wr
      vs-output-array-vec4-index-wr
    
    Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104143
    
    Signed-off-by: Gert Wollny <[hidden email]>
    Cc: <[hidden email]>
    Signed-off-by: Dave Airlie <[hidden email]>
    (cherry picked from commit 6c268ea79af80a65a89a23854bdbe8bc1e99ab23)
    
  • 47482090
    by Kenneth Graunke at 2017-12-08T18:27:00+00:00
    meta: Initialize depth/clear values on declaration.
    
    This helps avoid compiler warningss in the next commit - everything
    was initialized, but it wasn't obvious to static analysis.
    
    Suggested-by: Tapani Pälli <[hidden email]>
    (cherry picked from commit d6d16c02180929278dc49d3c9bdceece0aab189e)
    
  • 85724a9a
    by Kenneth Graunke at 2017-12-08T18:27:00+00:00
    meta: Fix ClearTexture with GL_DEPTH_COMPONENT.
    
    We only handled unpacking for GL_DEPTH_STENCIL formats.
    
    Cemu was hitting _mesa_problem() for an unsupported format in
    _mesa_unpack_float_32_uint_24_8_depth_stencil_row(), because the
    format was depth-only, rather than depth-stencil.
    
    Cc: "13.0 12.0" <[hidden email]>
    Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94739
    Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103966
    Reviewed-by: Tapani Pälli <[hidden email]>
    (cherry picked from commit 8705ed13e3114ad994dbd46387576749f54fc7eb)
    
  • 6c9c07b0
    by Alex Smith at 2017-12-08T18:27:00+00:00
    radv: Add LLVM version to the device name string
    
    Allows apps to determine the LLVM version so that they can decide
    whether or not to enable workarounds for LLVM issues.
    
    Signed-off-by: Alex Smith <[hidden email]>
    Cc: "17.2 17.3" <[hidden email]>
    Reviewed-by: Samuel Pitoiset <[hidden email]>
    Tested-by: Dieter Nützel <[hidden email]>
    (cherry picked from commit 8fda98c4f1dba2488b9e3ef3e820585f48a8a2f9)
    Signed-off-by: Emil Velikov <[hidden email]>
    
    Conflicts:
    	src/amd/vulkan/radv_device.c
    	src/amd/vulkan/radv_private.h
    
  • 773282c1
    by James Legg at 2017-12-08T18:27:00+00:00
    nir/opcodes: Fix constant-folding of bitfield_insert
    
    Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104119
    CC: <[hidden email]>
    CC: Samuel Pitoiset <[hidden email]>
    Reviewed-by: Matt Turner <[hidden email]>
    (cherry picked from commit 947470d10ba5ab11a75f0e19e124b189ff3fd8b2)
    
  • 63f44f2e
    by Ben Crocker at 2017-12-08T18:27:00+00:00
    docs/llvmpipe: document ppc64le as alternative architecture to x86.
    
    Power8, Power8NV, and Power9 are supported on an equal footing
    with X86.
    
    Cc: "17.2" "17.3" <[hidden email]>
    Signed-off-by: Ben Crocker <[hidden email]>
    Reviewed-by: Eric Engestrom <[hidden email]>
    
    [Eric: changed formatting, reworded a bit (with Ben's ack)]
    Signed-off-by: Eric Engestrom <[hidden email]>
    (cherry picked from commit 060eb314eb4e551cf870ad6a6e7e1363d4228efe)
    
  • 4473097d
    by Matt Turner at 2017-12-08T18:27:00+00:00
    i965/fs: Handle negating immediates on MADs when propagating saturates
    
    MADs don't take immediate sources, but we allow them in the IR since it
    simplifies a lot of things. I neglected to consider that case.
    
    Fixes: 4009a9ead490 ("i965/fs: Allow saturate propagation to propagate
                          negations into MADs.")
    Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103616
    Reported-and-Tested-by: Ruslan Kabatsayev <[hidden email]>
    Reviewed-by: Ian Romanick <[hidden email]>
    (cherry picked from commit a05af1f7b8f82a38513bba31f9573cd62d82f18d)
    
  • 1cb18fc9
    by Matt Turner at 2017-12-08T18:27:00+00:00
    util: Fix SHA1 implementation on big endian
    
    The code defines a macro blk0(i) based on the preprocessor condition
    BYTE_ORDER == LITTLE_ENDIAN. If true, blk0(i) is defined as a byte swap
    operation. Unfortunately, if the preprocessor macros used in the test
    are no defined, then the comparison becomes 0 == 0 and it evaluates as
    true.
    
    Fixes: d1efa09d342b ("util: import sha1 implementation from OpenBSD")
    Reviewed-by: Emil Velikov <[hidden email]>
    (cherry picked from commit 532674303a92c438cb1c48d224e9dee9dece91ec)
    
  • 6a698f7f
    by Matt Turner at 2017-12-08T18:27:00+00:00
    util: Fix disk_cache index calculation on big endian
    
    The cache-test test program attempts to create a collision (using key_a
    and key_a_collide) by making the first two bytes identical. The idea is
    fine -- the shader cache wants to use the first four characters of a
    SHA1 hex digest as the index.
    
    The following program
    
            unsigned char array[4] = {1, 2, 3, 4};
            int *ptr = (int *)array;
    
            for (int i = 0; i < 4; i++) {
                printf("%02x", array[i]);
            }
            printf("\n");
    
            printf("%08x\n", *ptr);
    
    prints
    
       01020304
       04030201
    
    on little endian, and
    
       01020304
       01020304
    
    on big endian.
    
    On big endian platforms reading the character array back as an int (as
    is done in disk_cache.c) does not yield the same results as reading the
    byte array.
    
    To get the first four characters of the SHA1 hex digest when we mask
    with CACHE_INDEX_KEY_MASK, we need to byte swap the int on big endian
    platforms.
    
    Bugzilla: https://bugs.freedesktop.org/103668
    Bugzilla: https://bugs.gentoo.org/637060
    Bugzilla: https://bugs.gentoo.org/636326
    Fixes: 87ab26b2ab35 ("glsl: Add initial functions to implement an
                          on-disk cache")
    Reviewed-by: Emil Velikov <[hidden email]>
    (cherry picked from commit c690a7a8cdfb6425547bbb782020098405851194)
    
  • 83c85b28
    by Eric Engestrom at 2017-12-08T18:27:00+00:00
    compiler: use NDEBUG to guard asserts
    
    nir_validate.c's #endif already had the correct NDEBUG comment
    
    Fixes: dcb1acdea00a8f2c29777 "nir/validate: Only build in debug mode"
    Fixes: 9ff71b649b4b3808a9e17 "i965/nir: Validate that NIR passes call nir_metadata_preserve()"
    Signed-off-by: Eric Engestrom <[hidden email]>
    Reviewed-by: Matt Turner <[hidden email]>
    (cherry picked from commit 7b85b9b8773b119360a31b66b321ae560a77cb6d)
    Signed-off-by: Emil Velikov <[hidden email]>
    
    Conflicts:
    	src/compiler/nir/nir.h
    
  • 14df2f2d
    by Kenneth Graunke at 2017-12-08T18:27:00+00:00
    i965: Fix Smooth Point Enables.
    
    We want to program the 3DSTATE_RASTER field to the gl_context value,
    not the other way around.
    
    Fixes: 13ac46557ab1 (i965: Port Gen8+ 3DSTATE_RASTER state to genxml.)
    
    Reviewed-by: Jason Ekstrand <[hidden email]>
    Reviewed-by: Lionel Landwerlin <[hidden email]>
    (cherry picked from commit 760e0156dfd5cf0281bc964a8090c792fc44ab16)
    
  • ecf8e4a6
    by Vadym Shovkoplias at 2017-12-08T18:27:00+00:00
    intel/blorp: Fix possible NULL pointer dereferencing
    
    Fix incomplete check of input params in blorp_surf_convert_to_uncompressed()
    which can lead to NULL pointer dereferencing.
    
    Fixes: 5ae8043fed2 ("intel/blorp: Add an entrypoint for doing
    bit-for-bit copies")
    Fixes: f395d0abc83 ("intel/blorp: Internally expose
    surf_convert_to_uncompressed")
    Reviewed-by: Emil Velikov <[hidden email]>
    Reviewed-by: Andres Gomez <[hidden email]>
    (cherry picked from commit cdb3eb7174f84f3200408c4b43c819fb093da9c6)
    [Emil Velikov: drop non-applicable x/y hunk]
    Signed-off-by: Emil Velikov <[hidden email]>
    
    Conflicts:
    	src/intel/blorp/blorp_blit.c
    
  • a5524802
    by Vadym Shovkoplias at 2017-12-08T18:27:00+00:00
    glx/dri3: Remove unused deviceName variable
    
    deviceName string is declared, assigned and freed but actually
    never used in dri3_create_screen() function.
    
    Fixes: 2d94601582e ("Add DRI3+Present loader")
    Signed-off-by: Vadym Shovkoplias <[hidden email]>
    Reviewed-by: Eric Engestrom <[hidden email]>
    (cherry picked from commit d5559292394f0e9b1c682baca05f81366fb389af)
    
  • 9c2f6658
    by Pierre Moreau at 2017-12-08T18:27:00+00:00
    nvc0/ir: Properly lower 64-bit shifts when the shift value is >32
    
    Fixes: 61d7676df77 "nvc0/ir: add support for 64-bit shift lowering on SM20/SM30"
    
    Fixes fs-shift-scalar-by-scalar.shader_test from piglit for the current
    set-up:
    
    uniform int64_t ival -0x7dfcfefbdf6536ff # bit pattern: 0x82030104209ac901
    uniform uint64_t uval 0x1400000085010203
    uniform int shl 36
    uniform int shr 36
    uniform int64_t iexpected_shl 0x09ac901000000000
    uniform int64_t iexpected_shr -0x7dfcff0 # bit pattern: 0xfffffffff8203010
    uniform uint64_t uexpected_shl 0x5010203000000000
    uniform uint64_t uexpected_shr 0x0000000001400000
    draw rect ortho 12 0 4 4
    
    Signed-off-by: Pierre Moreau <[hidden email]>
    Reviewed-by: Ilia Mirkin <[hidden email]>
    (cherry picked from commit 9bee12160bed72dae5cdb006ea38c40f89e174da)
    
  • f51950c4
    by Nicolai Hähnle at 2017-12-08T18:27:00+00:00
    radeonsi: fix the R600_RESOURCE_FLAG_UNMAPPABLE check
    
    The flag is on the pipe_resource, not the r600_resource.
    
    I don't see an obvious bug related to this, but it could potentially lead
    to suboptimal placement of some resources.
    
    Fixes: a41587433c4d ("gallium/radeon: add R600_RESOURCE_FLAG_UNMAPPABLE")
    Reviewed-by: Marek Olšák <[hidden email]>
    Tested-by: Dieter Nützel <[hidden email]>
    (cherry picked from commit 5e2962c9492e6a948516f6360f973e2e92034b01)
    
  • edd1f519
    by Timothy Arceri at 2017-12-08T18:27:00+00:00
    glsl: get correct member type when processing xfb ifc arrays
    
    This fixes a crash in:
    
    KHR-GL45.enhanced_layouts.xfb_block_stride
    
    Fixes: 0822517936d4 "glsl: add helper to process xfb qualifiers during linking"
    Reviewed-by: Kenneth Graunke <[hidden email]>
    (cherry picked from commit 9d53ccccb251d21f9291abaa3a28a41d06ce8c91)
    
  • df137dff
    by George Kyriazis at 2017-12-08T18:27:01+00:00
    swr: Handle resource across context changes
    
    Swr caches fb contents in tiles.  Those tiles are stored on a per-context
    basis.
    
    When switching contexts that share resources we need to make sure that
    the tiles of the old context are being stored and the tiles of the new
    context are being invalidated (marked as invalid, hence contents need
    to be reloaded).
    
    The context does not get any dirty bits to identify this case.  This has
    to be, then, coordinated by the resources that are being shared between
    the contexts.
    
    Add a "curr_pipe" hook in swr_resource that will allow us to identify a
    MakeCurrent of the above form during swr_update_derived().  At that time,
    we invalidate the tiles of the new context.  The old context, will need to
    have already store its tiles by that time, which happens during glFlush().
    glFlush() is being called at the beginning of MakeCurrent.
    
    So, the sequence of operations is:
    - At the beginning of glXMakeCurrent(), glFlush() will store the tiles
      of all bound surfaces of the old context.
    - After the store, a fence will guarantee that the all tile store make
      it to the surface
    - During swr_update_derived(), when we validate the new context, we check
      all resources to see what changed, and if so, we invalidate the
      current tiles.
    
    Fixes rendering problems with CEI/Ensight.
    
    Reviewed-by: Bruce Cherniak <[hidden email]>
    (cherry picked from commit b9aa0fa7d646f9ebb0a2e08d262c2eebfd875610)
    Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103732
    
  • 7d19ff0d
    by Juan A. Suarez Romero at 2017-12-08T18:27:01+00:00
    glsl: add varying resources for arrays of complex types
    
    This patch is mostly a patch done by Ilia Mirkin.
    
    It fixes KHR-GL45.enhanced_layouts.varying_structure_locations.
    
    v2: fix locations for TCS/TES/GS inputs and outputs (Ilia)
    
    CC: Ilia Mirkin <[hidden email]>
    Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103098
    Reviewed-by: Nicolai Hähnle <[hidden email]>
    Signed-off-by: Juan A. Suarez Romero <[hidden email]>
    (cherry picked from commit d5a641106baae2122cc3f09b4a755077d902ee88)
    
  • e5313572
    by Frank Richter at 2017-12-08T18:27:01+00:00
    gallium/wgl: fix default pixel format issue
    
    When creating a context without SetPixelFormat() don't blindly take the
    pixel format reported by GDI. Instead, look for our own closest pixel
    format.
    
    Minor clean-ups added by Brian Paul.
    
    Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103412
    Reviewed-by: Brian Paul <[hidden email]>
    Tested-by: Brian Paul <[hidden email]>
    (cherry picked from commit bf41b2b2627aa3790d380092c28c5d3395cc9cde)
    
  • 2a266cb6
    by Matt Turner at 2017-12-08T18:27:01+00:00
    i965/fs: Unpack count argument to 64-bit shift ops on Atom
    
    64-bit operations on Atom parts have additional restrictions over their
    big-core counterparts (validated by later patches).
    
    Specifically, the restriction that "Source and Destination horizontal
    stride must be aligned to the same qword" is violated by most shift
    operations since NIR uses a 32-bit value as the shift count argument,
    and this causes instructions like
    
       shl(8)          g19<1>Q         g5<4,4,1>Q      g23<4,4,1>UD
    
    where src1 has a 32-bit stride, but the dest and src0 have a 64-bit
    stride.
    
    This caused ~4 pixels in the ARB_shader_ballot piglit test
    fs-readInvocation-uint.shader_test to be incorrect. Unfortunately no
    ARB_gpu_shader_int64 test hit this case because they operate on
    uniforms, and their scalar regions are an exception to the restriction.
    
    We work around this by effectively unpacking the shift count, so that we
    can read it with a 64-bit stride in the shift instruction. Unfortunately
    the unpack (a MOV with a dst stride of 2) is a partial write, and cannot
    be copy-propagated or CSE'd.
    
    Bugzilla: https://bugs.freedesktop.org/101984
    (cherry picked from commit b541945c2027990ac571184bbf8e01285be0e33a)
    
  • ac78f7c7
    by Vinson Lee at 2017-12-08T18:27:01+00:00
    anv: Check if memfd_create is already defined.
    
    Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103909
    Signed-off-by: Vinson Lee <[hidden email]>
    Reviewed-by: Eric Engestrom <[hidden email]>
    (cherry picked from commit 8c1e4b1afc8d396ccf99c725c59b29a9aa305557)
    [Emil Velikov: resolve trivial conflicts]
    Signed-off-by: Emil Velikov <[hidden email]>
    
    Conflicts:
    	configure.ac
    	meson.build
    	src/intel/vulkan/anv_allocator.c
    
  • 3f1c8733
    by Denis Pauk at 2017-12-08T18:27:01+00:00
    gallium/{r600, radeonsi}: Fix segfault with color format (v2)
    
    Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102552
    
    v2: Patch cleanup proposed by Nicolai Hähnle.
        * deleted changes in si_translate_texformat.
    
    Cc: Nicolai Hähnle <[hidden email]>
    Cc: Ilia Mirkin <[hidden email]>
    
    Signed-off-by: Marek Olšák <[hidden email]>
    (cherry picked from commit 74d2456491fbd96eb3fb99cf8dd3595b223c2065)
    
  • d95c2edc
    by Julien Isorce at 2017-12-08T18:27:01+00:00
    st/va: change frame_idx from array to hash table
    
    The picture_id was assumed to be a frame number so in 0-31.
    But the vaapi client gstreamer-vaapi uses the surfaces handles
    as identifier which are unsigned int.
    
    This bug can happen when using a lot of vaapi surfaces within
    the same process. Indeed Mesa/st/va increments a counter for the
    surface ID: mesa/util/u_handle_table.c::handle_table_add which
    starts from 0 and incremented by 1 at each call.
    So creating more than 32 surfaces was a problem.
    
    The following bug contains a test that reproduces the problem
    by running a couple of vaapih264enc in the same process. The
    above also explains why there was no pb when running them in
    separated processes.
    
    Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102006
    Signed-off-by: Julien Isorce <[hidden email]>
    Tested-by: Tomas Rataj <[hidden email]>
    Acked-by: Christian König <[hidden email]>
    Reviewed-and-tested-by: Boyuan Zhang <[hidden email]>
    (cherry picked from commit 91d93aa62162f98d6377e5c796b63faa263f2c18)
    
  • 511cfe1d
    by Eric Anholt at 2017-12-08T18:27:01+00:00
    broadcom/vc4: Fix handling of GFXH-515 workaround with a start vertex count.
    
    We failed to take the start into account for how many vertices to draw in
    this round, so we would end up decrementing count below 0, which as an
    unsigned number meant we would loop until the CLs soon ran out of space.
    
    When I wrote the code I was thinking about how to use the previously
    emitted shader state (no index bias baked into the elements) by emitting
    up to 65535 and then only re-emitting with bias for the second wround, but
    that doesn't work if the start is over 65535.  Instead, just delay
    emitting shader state until we get into the drawarrays GFXH-515 loop and
    always bake the bias in when we're doing the workaround.
    
    (cherry picked from commit 84ab48c15c9373dfa4709f4f9e887c329286e5a1)
    
  • fe15da82
    by Fabian Bieler at 2017-12-08T18:27:01+00:00
    glsl: Match order of gl_LightSourceParameters elements.
    
    spotExponent and spotCosCutoff were swapped in the
    gl_builtin_uniform_element struct.
    Now the order matches across gl_builtin_uniform_element,
    glsl_struct_field and the spec.
    
    Reviewed-by: Brian Paul <[hidden email]>
    (cherry picked from commit 9bdb5457f4ecabd59e05d0b6cea1ff88bcb49d7f)
    
  • 07da9fd9
    by Fabian Bieler at 2017-12-08T18:27:01+00:00
    glsl: Fix gl_NormalScale.
    
    GLSL shaders can access the normal scale factor with the built-in
    gl_NormalScale.  Mesa's modelspace lighting optimization uses a different
    normal scale factor than defined in the spec.  We have to take care not
    to use this factor for gl_NormalScale.
    
    Mesa already defines two seperate states: state.normalScale and
    state.internal.normalScale.  The first is used by the glsl compiler
    while the later is used by the fixed function T&L pipeline.  Previously
    the only difference was some component swizzling.  With this commit
    state.normalScale always uses the normal scale factor for eyespace
    lighting.
    
    Reviewed-by: Brian Paul <[hidden email]>
    (cherry picked from commit c3ee464d7aa170225b5ec23b53a7f8d07663d428)
    
  • 267fe4f1
    by Nicolai Hähnle at 2017-12-08T18:27:01+00:00
    glsl: allow any l-value of an input variable as interpolant in interpolateAt*
    
    The intended rule has been clarified in GLSL 4.60, Section 8.13.2
    (Interpolation Functions):
    
       "For all of the interpolation functions, interpolant must be an l-value
        from an in declaration; this can include a variable, a block or
        structure member, an array element, or some combination of these.
        Component selection operators (e.g., .xy) may be used when specifying
        interpolant."
    
    For members of interface blocks, var->data.must_be_shader_input must be
    determined on-the-fly after lowering interface blocks, since we don't want
    to disable varying packing for an entire block just because one input in it
    is used in interpolateAt*.
    
    v2: keep setting must_be_shader_input in ast_function (Ian)
    v3: follow the relaxed rule of GLSL 4.60
    v4: only apply the relaxed rules to desktop GL
        (the ES WG decided that the relaxed rules may apply in a future version
         but not retroactively; see also
         dEQP-GLES31.functional.shaders.multisample_interpolation.interpolate_at_centroid.negative.*)
    
    Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101378
    Reviewed-by: Ian Romanick <[hidden email]> (v1)
    Reviewed-by: Timothy Arceri <[hidden email]>
    (cherry picked from commit 4f42450b86ea30f9228309e02ca68755c389866f)
    
  • 32b06912
    by Nicolai Hähnle at 2017-12-08T18:27:01+00:00
    glsl: fix interpolateAtXxx(some_vec[idx], ...) with dynamic idx
    
    The dynamic index of a vector (not array!) is lowered to a sequence of
    conditional assignments. However, the interpolate_at_* expressions
    require that the interpolant is an l-value of a shader input.
    
    So instead of doing conditional assignments of parts of the shader input
    and then interpolating that (which is nonsensical), we interpolate the
    entire shader input and then do conditional assignments of the interpolated
    result.
    
    Reviewed-by: Timothy Arceri <[hidden email]>
    (cherry picked from commit ca63a5ed3e9efb2bd645b425f7393089f4e132a6)
    
  • f76bea8a
    by Eduardo Lima Mitev at 2017-12-08T18:27:01+00:00
    glsl_parser_extra: Add utility to copy symbols between symbol tables
    
    Some symbols gathered in the symbols table during parsing are needed
    later for the compile and link stages, so they are moved along the
    process. Currently, only functions and non-temporary variables are
    copied between symbol tables. However, the built-in gl_PerVertex
    interface blocks are also needed during the linking stage (the last
    step), to match re-declared blocks of inter-stage shaders.
    
    This patch adds a new utility function that will factorize current code
    that copies functions and variables between two symbol tables, and in
    addition will copy explicitly declared gl_PerVertex blocks too.
    
    The function will be used in a subsequent patch.
    
    v2 (Neil Roberts):
    Allow the src symbol table to be NULL and explicitly copy the
    gl_PerVertex symbols in case they are not referenced in the exec_list.
    
    Reviewed-by: Kenneth Graunke <[hidden email]>
    Signed-off-by: Eduardo Lima Mitev <[hidden email]>
    Signed-off-by: Neil Roberts <[hidden email]>
    (cherry picked from commit 4c62a270a99d443316e29020377465a90a6968c0)
    
  • 2dc404f7
    by Eduardo Lima Mitev at 2017-12-08T18:27:01+00:00
    glsl: Use the utility function to copy symbols between symbol tables
    
    This effectively factorizes a couple of similar routines.
    
    v2 (Neil Roberts): Non-trivial rebase on master
    
    Reviewed-by: Kenneth Graunke <[hidden email]>
    Signed-off-by: Eduardo Lima Mitev <[hidden email]>
    Signed-off-by: Neil Roberts <[hidden email]>
    (cherry picked from commit f5fe99ac85e15b705612bd9e7599cc974c2a121b)
    
  • 62eb86dd
    by Eduardo Lima Mitev at 2017-12-08T18:27:01+00:00
    glsl/linker: Check that re-declared, inter-shader built-in blocks match
    
    >From GLSL 4.5 spec, section "7.1 Built-In Language Variables", page 130 of
    the PDF states:
    
        "If multiple shaders using members of a built-in block belonging to
         the same interface are linked together in the same program, they must
         all redeclare the built-in block in the same way, as described in
         section 4.3.9 “Interface Blocks” for interface-block matching, or a
         link-time error will result."
    
    Fixes:
    * GL45-CTS.CommonBugs.CommonBug_PerVertexValidation
    
    v2 (Neil Roberts):
    Explicitly look for gl_PerVertex in the symbol tables instead of
    waiting to find a variable in the interface.
    
    Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102677
    Reviewed-by: Kenneth Graunke <[hidden email]>
    Signed-off-by: Eduardo Lima Mitev <[hidden email]>
    Signed-off-by: Neil Roberts <[hidden email]>
    (cherry picked from commit f9de7f55969e981f6e98a41fce04bc3a2a8280eb)
    
  • 32003057
    by Emil Velikov at 2017-12-14T13:17:30+00:00
    Update version to 17.2.7
    
    Signed-off-by: Emil Velikov <[hidden email]>
    
  • 834c36fa
    by Emil Velikov at 2017-12-14T13:27:23+00:00
    docs: add release notes for 17.2.7
    
    Signed-off-by: Emil Velikov <[hidden email]>
    
  • 9ca5f557
    by Emil Velikov at 2017-12-14T13:49:09+00:00
    docs: add sha256 checksums for 17.2.7
    
    Signed-off-by: Emil Velikov <[hidden email]>
    
  • 2186a9ee
    by Matt Turner at 2017-12-20T16:16:47+02:00
    util: Assume little endian in the absence of platform-specific handling
    
    (cherry picked from commit 6a353479a7577dcff7c7a31809f27b59270648fb)
    
    Squashed with:
    
    util: Use preprocessor correctly
    
    Fixes: 6a353479a757 ("util: Assume little endian in the absence of
                          platform-specific handling")
    (cherry picked from commit b8cbad624b8198949d63c0211fe4925fc3bb9a7a)
    
    Squashed with:
    
    util: Just give up and define PIPE_ARCH_LITTLE_ENDIAN on MSVC
    
    MSVC doesn't support #warning?! Getting really tired of this.
    
    (cherry picked from commit 676761252b731a6bf408e4dca694c31d74a995fc)
    
    Squashed with:
    
    util: Also include endian.h on cygwin
    
    If u_endian.h can't determine the endianess, the default behaviour in sha1.c
    is to build for big-endian
    
    Signed-off-by: Jon Turney <[hidden email]>
    Reviewed-by: Matt Turner <[hidden email]>
    (cherry picked from commit 2c62ccb10a7f3a2962f51688a3ae957254c5ce9b)
    
  • e0160dd3
    by Matt Turner at 2017-12-20T19:40:22+02:00
    util: Add a SHA1 unit test program
    
    Reviewed-by: Emil Velikov <[hidden email]>
    (cherry picked from commit 513d7ffa23d42e96f831148fa13bf470087424c3)
    (cherry picked from commit 60ed1a07f2991306131781cf0ec01b25f54b72c9)
    
    Squashed with:
    
    util: scons: wire up the sha1 test
    
    Signed-off-by: Emil Velikov <[hidden email]>
    Reviewed-by: Andres Gomez <[hidden email]>
    (cherry picked from commit 5d03a68640dcf216484e37c316d2d91db9994a66)
    (cherry picked from commit 455ff75892a49bd2141ffeb3654fec64cd4c4143)
    
  • 2e659380
    by Leo Liu at 2017-12-20T19:40:38+02:00
    radeon/vce: move destroy command before feedback command
    
    VCE processing IBs starts from session and task info at first level,
    other commands processed subsequently. The task info for destroy is
    embedded to destroy command, resulting that feedback command is not
    properly procoessed. This is causing kernel spin VM fault messages on
    Polaris and Vega10 card when running ends at encode application.
    
    The fix is also verified on VCE physical mode card.
    
    Signed-off-by: Leo Liu <[hidden email]>
    Cc: [hidden email]
    Acked-by: Christian König <[hidden email]>
    (cherry picked from commit 6d74cb2570eb919c72e519e590d2464757465902)
    
  • 8f8b5c0a
    by Bas Nieuwenhuizen at 2017-12-20T19:40:38+02:00
    spirv: Fix loading an entire block at once.
    
    There is no chain, so  checking the length ends with a SEGFAULT.
    
    Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103579
    Cc: <[hidden email]>
    Reviewed-by: Emil Velikov <[hidden email]>
    Reviewed-by: Jason Ekstrand <[hidden email]>
    (cherry picked from commit b926da241a4221376afe195c476f6a05621e5c75)
    [Andres Gomez: 16 bits types and vtn_assert/fail not yet in 17.2]
    Signed-off-by: Andres Gomez <[hidden email]>
    
    Conflicts:
    	src/compiler/spirv/vtn_variables.c
    
  • 9f94d6aa
    by Brian Paul at 2017-12-20T19:40:38+02:00
    xlib: call _mesa_warning() instead of fprintf()
    
    We use _mesa_warning() everywhere else in this code.  Change requested
    by Rick Irons of Mathworks.
    
    CC: <[hidden email]>
    Reviewed-by: Ian Romanick <[hidden email]>
    (cherry picked from commit 7a46063803c51e74e635a7d6e056b6442b8f2c5a)
    
  • 5ffdc3a2
    by Roland Scheidegger at 2017-12-20T19:40:38+02:00
    r600: use min_dx10/max_dx10 instead of min/max
    
    I believe this is the safe thing to do, especially ever since the driver
    actually generates NaNs for muls too.
    The ISA docs are not very helpful here, however the dx10 versions will pick
    a non-nan result over a NaN one (this is also the ieee754 behavior), whereas
    the non-dx10 ones will pick the NaN (verified by newly changed piglit
    isinf-and-isnan test).
    Other "modern" drivers will most likely do the same.
    This was shown to make some difference for bug 103544, albeit it is not
    required to fix it.
    
    Reviewed-by: Dave Airlie <[hidden email]>
    (cherry picked from commit aab0bfc648bf1be50b81a25224970015f1dc78b8)
    
  • 3730b04e
    by Roland Scheidegger at 2017-12-20T19:40:38+02:00
    r600: use DX10_CLAMP bit in shader setup
    
    The docs are not very concise in what this really does, however both
    Alex Deucher and Nicolai Hähnle suggested this only really affects instructions
    using the CLAMP output modifier, and I've confirmed that with the newly
    changed piglit isinf_and_isnan test.
    So, with this bit set, if an instruction has the CLAMP modifier bit (which
    clamps to [0,1]) set, then NaNs will be converted to zero, otherwise the result
    will be NaN.
    D3D10 would require this, glsl doesn't have modifiers (with mesa
    clamp(x,0,1) would get converted to such a modifier) coupled with a
    whatever-floats-your-boat specified NaN behavior, but the clamp behavior
    should probably always be used (this also matches what a decomposition into
    min(1.0, max(x, 0.0)) would do, if min/max also adhere to the ieee spec of
    picking the non-nan result).
    Some apps may in fact rely on this, as this prevents misrenderings in
    This War of Mine since using ieee muls
    (ce7a045feeef8cad155f1c9aa07f166e146e3d00), without having to use clamped
    rcp opcode, which would also fix this bug there.
    radeonsi also seems to set this bit nowadays if I see that righ (albeit the
    llvm amdgpu code comment now says "Make clamp modifier on NaN input returns 0"
    instead of "Do not clamp NAN to 0" since it was changed, which also looks
    a bit misleading).
    
    v2: set it in all shader stages.
    
    Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103544
    
    Reviewed-by: Dave Airlie <[hidden email]>
    (cherry picked from commit 3835009796166968750ff46cf209f6d4208cda86)
    
  • 334ae3b0
    by Brian Paul at 2017-12-20T19:40:38+02:00
    gallium/aux: include nr_samples in util_resource_size() computation
    
    This function is only used in two places:
    1. VMware driver, but only for HUD reporting
    2. st/nine state tracker, used for texture memory accounting
    
    Fixes: a69efa9482d ("util: add new util_resource_size() function in
    u_resource.[ch]")
    
    Reviewed-by: Roland Scheidegger <[hidden email]>
    Reviewed-by: Charmaine Lee <[hidden email]>
    Reviewed-by: Marek Olšák <[hidden email]>
    (cherry picked from commit dde8309cdea5c739983693650105b2f993c5a71c)
    
  • a8ee7222
    by Bas Nieuwenhuizen at 2017-12-20T19:40:38+02:00
    radv: Fix multi-layer blits.
    
    We did not set the layer correctly for the dst, as we would keep
    using the base layer. Same for the source image.
    
    Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102710
    CC: <[hidden email]>
    Reviewed-by: Dave Airlie <[hidden email]>
    (cherry picked from commit b42e106d4dfa61a6351b076741c5458b5677f332)
    
  • 5226e377
    by Iago Toral Quiroga at 2017-12-20T19:40:38+02:00
    i965/vec4: use a temp register to compute offsets for pull loads
    
    64-bit pull loads are implemented by emitting 2 separate
    32-bit pull load messages, where the second message loads from
    an offset at +16B.
    
    That addition of 16B to the original offset should not alter the
    original offset register used as source for the pull load instruction
    though, since the compiler might use that same offset register in other
    instructions (for example, for other pull loads in the shader code
    that take that same offset as reference).
    
    If the pull load is 32-bit then we only need to emit one message and
    we don't need to do offset calculations, but in that case the optimizer
    should be able to drop the redundant MOV.
    
    Fixes the following test on Haswell:
    KHR-GL45.gpu_shader_fp64.fp64.max_uniform_components
    
    Reviewed-by: Matt Turner <[hidden email]>
    Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103007
    (cherry picked from commit 8620f7ebbc763dc1bbbc825d31cacfdd84433e05)
    
  • aa874286
    by Andres Gomez at 2017-12-20T19:40:38+02:00
    cherry-ignore: swr: Fix KNOB_MAX_WORKER_THREADS thread creation override.
    
    stable: This commit addressed earlier commit ead0dfe31ec7 which did
    not land in branch.
    
    Signed-off-by: Andres Gomez <[hidden email]>
    
  • fb342ac0
    by Andres Gomez at 2017-12-20T19:40:38+02:00
    cherry-ignore: added 17.3 nominations.
    
    stable: 17.3 nominations only.
    
    Signed-off-by: Andres Gomez <[hidden email]>
    
  • dd0b6dfd
    by Andres Gomez at 2017-12-20T19:40:38+02:00
    cherry-ignore: radv: port merge tess info from anv
    
    fixes: This commit addressed earlier commit d1c9f30d7ff7 which did not
    land in branch.
    
    Signed-off-by: Andres Gomez <[hidden email]>
    
  • 03538c21
    by Andres Gomez at 2017-12-20T19:40:38+02:00
    cherry-ignore: main: Clear shader program data whenever ProgramBinary is called
    
    extra: The commit just references a fix for an additional change in
    its v2.
    
    Signed-off-by: Andres Gomez <[hidden email]>
    
  • d9dd945d
    by Andres Gomez at 2017-12-20T19:40:38+02:00
    cherry-ignore: r600: set DX10_CLAMP for compute shader too
    
    extra: The commit references a previous commit in which the changes
    should have been included but, as clarified by the developer, it is
    not needed for stable.
    
    Signed-off-by: Andres Gomez <[hidden email]>
    
  • fb618171
    by Andres Gomez at 2017-12-22T22:34:12+02:00
    Update version to 17.2.8
    
    Signed-off-by: Andres Gomez <[hidden email]>
    
  • 34827907
    by Andres Gomez at 2017-12-22T22:39:47+02:00
    docs: add release notes for 17.2.8
    
    Signed-off-by: Andres Gomez <[hidden email]>
    
  • 341f6e50
    by Timo Aaltonen at 2018-01-17T17:28:45+02:00
    Merge tag 'mesa-17.2.8' into ubuntu-artful
    
    mesa-17.2.8
    
  • 80bebf07
    by Timo Aaltonen at 2018-01-17T17:39:26+02:00
    release to artful
    

30 changed files:

The diff was not included because it is too large.